In debugging and optimizing processor systems it is often desired to be able to monitor the performance of the processor. Some modern microprocessors therefore include performance monitoring hardware (also called “performance monitors”). The performance monitor circuitry is disposed on the same integrated circuit chip along with the microprocessor itself and may even be considered part of the microprocessor. A user who is debugging the system can use the performance monitor hardware on the microprocessor to collect diagnostic information about the operation of the processor. The user may, for example, set traps or halt the microprocessor at certain locations in the microprocessor code. The user can also use the performance monitor to collect state information at various points in the operation of the processor. The user can also collect histogram data indicating how much time the microprocessor spends executing in each of several different parts of the code.
U.S. Pat. No. 6,351,724 discloses a microprocessor that includes a performance monitor. The performance monitor includes, among other things, a bus monitor unit and a memory unit. The bus monitor unit is coupled to the address, data and control lines of the microprocessor. A data acquisition period is divided into a number of histogram time periods. As the microprocessor operates and executes instructions, the bus monitor unit detects when one of up to sixty-four user-definable events occurs. The performance monitor may also store the number of times a particular user-defined event occurs during each of a plurality of histogram time periods. The event count is stored into one of a plurality of memory locations that corresponds to the associated histogram time period. The stored event counts form a sort of histogram. After the acquisition period is over, the stored contents of the memory locations can be read out from the performance monitor and analyzed during the debugging of the processor system.
Although the events detected by the performance monitor of U.S. Pat. No. 6,351,724 are selectable by the user, the capabilities of the performance monitor are quite limited. The performance monitor circuit is to be embodied in each microprocessor manufactured and sold. Making a larger and more flexible performance monitor having more capabilities might be nice from the perspective of the person debugging the system, but the added cost of having to provide the necessary such hardware on each microprocessor integrated circuit serves to limit the economically realizable capabilities of the performance monitor.
U.S. Pat. No. 5,867,644 discloses another user-configurable performance monitor that is disposed on the same chip with a microprocessor. The performance monitor includes a programmable state machine, a plurality of on-chip input sources, and a plurality of counters. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements, and can be configured by the user to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the user may change the information against which the state of the nodes is compared.
The output devices include a plurality of counters. The state machine can, for example, be configured to increment a particular counter so that the counter functions as an event counter that keeps a tally of the number of times a certain user-defined event has occurred. A signal output by a counter may be used as a input to the state machine, so that one event may be defined as a function of a different event having occurred a certain number of times. By configuring the performance monitor appropriately, the user can generate triggers that halt the microprocessor, trap the microprocessor and/or latch the states of numerous test nodes within the microprocessor in “sample-on-the-fly” fashion.
Despite the fact that the performance monitor is user-configurable, its configurability is limited. There are, for example, a fixed number of output counters that can operate as event counters. The number of bits in each counter is not freely adjustable. Each counter is realized in dedicated hardware and therefore has a predetermined number of bits. There are a fixed number of comparators, and each comparator can compare values of a fixed number of bits. The state machine is programmable, but the number of states that the state machine can have is limited by the fixed number of sequential logic elements provided for this purpose. Added functionality in the performance monitor cannot be provided without increasing the amount of semiconductor die area dedicated to the performance monitor and without increasing the cost of the microprocessor integrated circuit. The user of such a performance monitor is therefore sometimes stuck having to make do with a general purpose and limited function performance monitor that is not necessarily optimal for the user's diagnostic purpose.
An improved, more flexible and more cost-effective performance monitoring capability is sought.